diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a3..913537d 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------